Differential Latency Mitigation in FPGA-Based Low-Latency Trading Engines

Architect a hardware-based packet filtering pipeline on a Field Programmable Gate Array (FPGA) that achieves sub-microsecond deterministic latency when processing high-frequency data streams. Implement a jitter-reduction mechanism to handle asynchronous signal propagation across clock domains while maintaining high throughput under 95% line saturation. Verify the solution using a testbench that introduces variable input clock drift to stress test the synchronization logic.