Asynchronous Memory Interconnect Arbiter

Design and implement a robust hardware arbiter for a multi-master bus system that resolves requests using a fair round-robin scheduling algorithm with priority-based preemption. You must simulate the logic using a hardware description language and verify timing closure under non-deterministic latency constraints common in asynchronous clock domain crossings. The final solution must demonstrate minimized jitter and zero-deadlock state transitions under high-load synthetic traffic patterns.